This application claims the priority benefit of Taiwan application serial no. 89114791, filed Jul. 24, 2000.
1. Field of the Invention
The invention relates in general to a method of photolithography using super-resolution near-field structure. More particularly, this invention relates to a method of photolithography using super-resolution near-field structure to form a pattern with a smaller line width on a photoresist layer.
2. Description of the Related Art
Photolithography process is one of the most crucial steps in semiconductor fabrication process. Through photolithography, the layout of the integrated circuit can be transferred into the semiconductor chip. Typically, a pattern is designed on a photomask. Via exposure and etching processes, the pattern is transferred from the photomask to the photoresist layer with a certain proportion.
Referring to FIG. 1 to FIG. 4, a conventional photolithography process to pattern dimensions and positions of a metal line on a semiconductor chip is shown. In FIG. 1, a semiconductor chip 10 comprises a substrate 22 and a photoresist layer 24 formed on the substrate 22. The substrate 22 further comprises a silicon substrate 12, doped regions 14 on the silicon substrate 12, an insulating layer 16 formed of silicon oxide compound on the silicon substrate 12. Contact plugs 18 are formed in the insulating layer 16 to electrical connect the doped regions 18 and a metal layer 20 formed on the insulating layer 16.
A positive or negative photoresist layer 24 is formed is formed on the metal layer 20. When a positive photoresist layer is used, during the photochemical transformation of the exposure process, a light beam penetrates through the photomask pattern to be incident onto the photoresist layer 24. The portion of the photoresist layer which has not been incident by the light beam is remained by development and cleaning process, while the portion of the photoresist layer which has exposed is removed. A hard mask with the identical pattern on the photomask is thus formed on the semiconductor chip 22. In contrast, if a negative photoresist layer is in use, the exposed portion is to be remained, while the portion which has not be exposed is to be removed during the subsequent development and cleaning process. In this conventional method illustrated in FIG. 1 to FIG. 4, a positive photoresist layer is used as an example.
In FIG. 2, a photomask 30 including a transparent glass or quartz substrate 32 is provided. Non-transparent chromium pattern 34 are formed on the substrate 32. After the pattern is formed, an exposure step is performed on the photoresist layer 24 using the photomask 30. The semiconductor chip 10 is then disposed in a developer to perform a development step. Referring to FIG. 3, a top view of the semiconductor chip 10 is shown. After the development step, several cleaning steps are required to remove the developer and the resolved positive photoresist layer 24 on the semiconductor chip 10. As shown in FIG. 4, after the cleaning steps, an etching step is performed using the remaining photoresist layer 26 as a hard mask to remove the metal layer 24 which has not been covered by the remaining photoresist layer 26 until the insulating layer 16 is exposed. The remaining photoresist layer 26 is then removed, followed by formation of the patterned metal lines 28 in contact with the metal plugs 18.
As the complexity and integration keep increasing, the pattern 32 on the photomask 30 has to be designed smaller and smaller. However, while transferring the pattern, the critical dimension of the pattern transferred by exposure is restricted to the resolution limit of the optical exposure tool. As a result, while performing exposure to transfer a high density photomask pattern 34 into the photoresist pattern 26 on the semiconductor chip 10, optical proximity effect is easily to occur. The photoresist layer is thus over exposed or under exposed to cause resolution loss. The critical dimension of the pattern is consequently shrunk result in a transferred photoresist pattern that is not identical to the photomask pattern. The device performance is thus seriously affected.
The invention provides a method of photolithography using super-resolution near-field structure to form a pattern with a narrow line width.
A method of photolithography using a super-resolution near-field structure is provided. The method of photolithography is applied to pattern a photoresist pattern on a semiconductor chip. The semiconductor chip comprises a substrate and a photoresist layer on the substrate. A super-resolution near-field structure is formed on the photoresist layer. The super-resolution near-field structure comprises a first dielectric layer, a second dielectric layer and an active layer sandwiched between the first and the second dielectric layer. A light beam is incident on the semiconductor chip. The light beam transmits through the super-resolution near-field structure to expose the photoresist layer. Transmitting through the super-resolution near-field structure, the light intensity of the light beam is increased, while the aperture thereof is reduced.
In the invention, using the super-resolution near-field structure, the aperture of the exposure light source can be reduced, and the light intensity can be increased to breakthrough the resolution limit of a machine. Thus, to form a photoresist layer with a line width breaking the resolution limit is possible. By adjusting the thickness of the thin film of the super-resolution near-field structure, the aperture of the exposure light source can be shrunk, the dimension of the exposed spot on the photoresist layer is no more restricted by the resolution limit of the exposure machine.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.